In the fabrication of microelectronic devices, application of one or more metallization layers is an important step in the overall fabrication process. The metallization may be used in the formation of discrete microelectronic components, but is most often used to provide interconnect components formed on a workpiece, such as a semiconductor wafer. For example, metallized structures are used to interconnect devices of an integrated circuit.
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor. Devices which may be formed within the semiconductor include MOS transistors, bipolar transistors, diodes, and diffused resistors. Devices which may be formed within the dielectric include thin film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 200 mm diameter silicon wafer. The devices utilized in each die are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. Aluminum alloy and silicon oxide are examples of materials which have been used for conductive and dielectric features.
With the continuing interest by integrated circuit manufacturers for ways to reduce delays in the propagation of electrical signals, copper has replaced aluminum alloy as the material of choice for interconnect structures.
In addition to its desirable electrical properties, the use of copper as interconnect structures allows integrated circuit manufacturers to leverage electrodeposition process advantages provided by the use of copper. For example, electrodeposition of copper currently provides the most cost-effective manner in which to deposit a copper metallization layer. In addition to being economically viable, electrodeposition techniques provide substantially conformal copper films that are mechanically and electrically suitable for interconnect structures.
Despite the advantages of copper, it has not been as widely used as an interconnect material as one would expect. This is due, at least in part, to the difficulty in effectively and economically depositing copper metallization. For example, depositing copper metallization necessitates the need for the presence of barrier layer materials. The need for barrier layer materials arises from the tendency of copper to diffuse into silicon junctions and alter the electrical characteristics of the semiconductor devices formed in the substrate. Barrier layers made of, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten and tungsten nitride, and the like, are typically laid over the silicon junctions and any intervening layers prior to depositing a layer of copper. Unfortunately, materials used as barrier layers typically do not exhibit the electrical conductive properties necessary to allow for the uniform electrochemical deposition of copper directly onto the barrier layers using conventional gap fill chemistries and processes. Accordingly, current practice employs a conductive seed layer applied to the barrier layer before the workpiece is subjected to an electrochemical copper deposition process.
A number of processes for applying a conductive seed layer onto the barrier layer exist. One such process is chemical vapor deposition or CVD, in which a thin copper film is formed on the surface of the barrier layer by thermal decomposition and/or reaction of gas phase copper compositions. CVD can result in conformal copper coverage over a variety of topological profiles; however, CVD is expensive to carry out and utilizes expensive equipment.
Another known technique for depositing a seed layer onto the barrier layer is physical vapor deposition or PVD. PVD provides relatively good adhesion between the barrier layer and the deposit of copper seed layer when compared to a seed layer deposited by CVD. One disadvantage of PVD is that it may result in poor (nonconformal) step coverage when used to fill recessed micro-structures, such as vias and trenches, disposed in the surface of the semiconductor workpiece.
The need to deposit a seed layer using CVD or PVD as described above introduces a process step that requires a large capital investment in equipment to carry out the vapor deposition process. In addition, both PVD and CVD are considered to be relatively slow, thus adversely affecting manufacturing throughput.
Attempts have been made to electrodeposit copper directly onto a barrier layer of titanium nitride or titanium tungsten. However, it has been observed by the present inventors that electrochemical deposition of copper directly onto untreated barrier layers leads to unsatisfactory results, such as poor nucleation and copper peeling due to poor adhesion between the electrodeposited copper and the material of the barrier layer.
In view of the above, the inventors have recognized the need to provide processes for depositing copper onto barrier layers that provide conformal copper coverage with adequate adhesion to the barrier layer, provide adequate deposition rates, are commercially viable, and which do not employ seed layers deposited by PVD or CVD. These needs are met by the processes of the present invention as described below.